This disclosure relates to data processing and storage, and more specifically, to data storage systems, such as flash-based data storage systems, that employ multiple data retrieval mechanisms.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor. In a typical implementation, a NAND flash memory array is organized in blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays can generally be programmed on a page basis, but are erased on a block basis.
NAND flash memory-based storage systems provide numerous benefits over conventional magnetic hard disk drive storage systems. These benefits include greater reliability, faster access times, and lower power consumption. In addition, NAND flash memory-based storage systems provide more consistent performance in that servicing input/output operations (IOPs) does not require any mechanical movement (e.g., a magnetoresistive head seeking the target sector of a magnetic disk), and therefore IOPs can generally all be serviced in approximately the same amount of time. Response times can begin to vary, however, in NAND flash memory-based storage systems as the number of pending IOPs increases, for example, due to queuing delays and delays attributable to the garbage collection process utilized to reclaim and consolidate valid data from memory blocks selected for erasure.
The present disclosure recognizes that although the average response time of a NAND flash memory-based storage system may remain relatively low in the presence of occasional accesses having longer response times, the inconsistency between IOP response times can contribute to undesirable host behavior, such as an application timing out while waiting on a long latency IOP to complete. Consequently, the present disclosure recognizes that it would be beneficial and desirable to promote a tighter distribution of IOP response times in a NAND flash memory-based storage system.